The escalating requirements for high densification and performance associated with ultra large scale integration semiconductor devices require design features of 0.25 microns and under, such as 0.18 microns and under, increased transistor and circuit speeds, high reliability and increased manufacturing throughput for competitiveness. The reduction of design features to 0.25 microns and under challenges the limitations of conventional semiconductor manufacturing technology.
The aggressive scaling of gate electrode dimensions into the deep submicron regime, such as less than about 0.25 microns, demands extremely shallow junctions in order to maintain good short channel characteristics and current drive. For example, semiconductor devices having design features of about 0.25 microns require a significantly reduced lightly doped drain (LDD) junction depth (X.sub.J) of less than about 800 .ANG.. Conventional methodology comprises ion implanting an N-type impurity having a low diffusion coefficient, typically arsenic (As). However, the formation of a sharp N-type impurity (N)-LDD junction requires the power supply voltage (V.sub.dd) to be reduced in order to maintain sufficient hot carrier reliability. While attractive from a power dissipation standpoint, a lower V.sub.dd compromises speed and current drive required for microprocessors particularly for desktop applications. Thus, hot carrier injection (HCI) reliability has become the limiting factor for performance of N-channel MOSFETs, particularly as the design rules shrink. A reduction in the HCI lifetime is attributed to the sharp N-LDD junction which results in a high peak electric field in the channel region.
D. Nayak et al., in "A Comprehensive Study of Performance and Reliability of P, As, and Hybrid As/P N-LDD Junctions for Deep-Submicron CMOS Logic Technology," IEEE Electron Device Letters, Vol. 18, No. 6, 1997, pp. 281-283, disclose a method of N-LDD junction grading to decrease the peak electric field in the channel, thereby improving the HCI lifetime. The disclosed technique comprises ion implanting As and P to form the N-LDD implant. While this technique was reported to improve the HCI lifetime in semiconductor devices having 0.35 micron technology, such a hybrid As/P-LDD technique cannot be directly applied to semiconductor devices having design features of about 0.25 microns and below, because the Off-current is increased to an unacceptably high level.
In copending application Ser. No. 08/923,996 filed on Sep. 5, 1997, a method of reducing capacitance loading is disclosed wherein a rapidly diffusing N-type impurity, such as P, is implanted into the source/drain region employing a double spacer technique. In copending application Ser. No. 08/979,364 filed on Nov. 26, 1997, a method of forming a graded N-LDD junction is disclosed, which method comprises plural ion-implantations at different dosages and different angles to the semiconductor substrate.
There exists a need for semiconductor methodology and devices wherein the HCI lifetime of a MOSFET is increased without increasing the Off-current. There exists an even greater need for semiconductor methodology and devices having a design rule of about 0.25 microns and under with an increased HCI lifetime without an attendant increased Off-current.